FIG. 1 is a circuit diagram showing the configurations of a memory cell 100 and a peripheral circuit in a typical CMOS (Complementary Metal-Oxide Semiconductor) type of SRAM. With reference to FIG. 1, the memory cell 100 contains a positive feedback loop (flip-flop) of two CMOS inverters INV10 and INV20; and two N-channel MOS transistors N110 and N120 (hereinafter, to be referred to as selection transistors N110 and N120) for controlling connection between each of bit lines BL10 and BL20 and one of the inverters INV10 and INV20. In detail, the two inverters INV10 and INV20 are connected between a first power supply voltage VDD and a second power supply voltage (GND). The output of the inverter INV10 is connected to the input of the inverter INV20 through a node ND110, and the output of the inverter INV20 is connected to the input of the inverter INV10 through a node ND120. The node ND110 is connected to the bit line BL10 through the selection transistor N110 whose gate is connected to a word line WL100, and the node ND120 is connected to the bit line BL20 through the selection transistor N120 whose gate is connected to the word line WL100.
When the word line WL100 is activated, the selection transistors N110 and N120 are turned on, and the node pairs ND110 and ND120 are electrically connected to the bit lines BL10 and BL20, respectively. Consequently, the nodes ND110 and ND120 hold the voltages supplied from the bit lines BL10 and BL20, respectively (Data Write). Or, the voltages held by the nodes ND110 and ND120 are supplied to a sense amplifier (not shown) through the bit lines BL10 and BL20. The sense amplifier compares the input voltage with a threshold and determines the value of a data (Data Read). In this way, the write of the data to the memory cell 100 or the read of the data from the memory cell 100 is carried out.
Also, before the data is written and read, the pair of bit lines BL10 and BL20 is pre-charged to the power supply voltage VDD by a pre-charging circuit 200. The pre-charging circuit 200 contains P-channel MOS transistors P10 and P20 (hereinafter, to be referred to as pre-charge transistors P10 and P20), which electrically connect the first power supply voltage VDD and the bit line pairs BL10 and BL20, on the basis of a pre-charge control signal PRB10 supplied to the gates.
When a read test is performed on the SRAM configured as mentioned above, there is a case that a memory cell, in which SNM (Static Noise Margin) is small and a defect generation rate is high, cannot be detected as a defect cell.
The operation of a conventional read test and its problem will be described below with reference to FIGS. 1 and 2. FIG. 2 shows timing charts in the conventional read test.
Until a time T1, “1” is written to the node ND110, and “0” is written to the node ND120. At the time T1, the pre-charge control signal PRB10 is changed to a low level, so that the bit lines BL10 and BL20 are pre-charged to a high level. At a time T2, the pre-charge control signal PRB10 is changed to the high level, so that the connection between each of the bit lines BL10 and BL20 and the first power supply VDD is disconnected. Also, the word line WL100 is activated to select the memory cell. Thus, the data written in the memory cell 100 is read.
In the period between the time T2 and a time T3 at which the word line WL100 is inactivated, the voltage of the node ND120 that holds the data “0” is increased by the bit line BL20 pre-charged to the high level. Here, if the memory cell 100 is in a normal state, the voltage of the node ND120 is increased only to a voltage lower than the logical threshold voltage of the inverter INV10. For this reason, the voltage of the node ND120 returns to the low level (the data “0”) in association with the discharging of the bit line BL20. In this case, the data read until the time T3 is the same as the write data, and the memory cell is determined to be in the normal state. On the other hand, if the memory cell 100 is in an abnormal state, the voltage of the node ND120 exceeds the logical threshold voltage of the inverter INV10, the inverted data different from the write data is read (not shown). In this case, the memory cell is determined to be in the abnormal state.
However, even if the memory cell 100 is in the abnormal state, there is a case that the voltage of the node ND120 is increased only to the voltage lower than the logical threshold voltage of the inverter INV10, so that the write data is not inverted. This is for the reason why the charges on the bit line BL20 are fast discharged when the data is read out, as compared with the voltage increase of the node ND120. In this way, even if the memory cell 100 is in the abnormal state, there is a case that the same data is as the write data is read out and the operation is determined to be no error (normal).
The same operation as in the period between the times T1 and T3 is repeated in the period between the times T3 and T5.
As mentioned above, there is a case that the memory cell in the abnormal state cannot be detected even if the SNM is checked by the conventional read test method. A test circuit for solving such a problem is described in, for example, “Weak Write Test Mode: An SRAM Cell Stability Design for Test Technique” (International test conference, 1997) by Anne Meixner, Jash Banik (Non-Patent Literature 1).
The operation of a read test using the testing circuit described in the non-patent document 1 will be described below with reference to FIGS. 3 and 4. FIG. 3 is a circuit diagram showing the configurations of a memory cell 100 and a peripheral circuit (a pre-charging circuit 200 and a testing circuit 300) that are described in the non-patent document 1. FIG. 4 shows timing charts in a read test that uses the testing circuit 300 described in the non-patent document 1.
The operation between a test start and a time T2 are same as the operation of the conventional example shown in FIG. 2. At the time T2, the pre-charge control signal PRB10 is changed to the high level, and the word line WL100 is activated, and the memory cell is selected. At this time, a control signal WR0 supplied to the testing circuit 300 is switched to the high level, and a control signal WR1 is switched to the low level. Consequently, the voltage of the bit line BL20 is increased to the first power supply voltage VDD, and the voltage of the bit line BL10 is decreased to the GND voltage.
Since the voltage of the node ND120 is increased and the voltage of the node ND110 is decreased, the logical threshold voltage of the inverter INV10 is decreased as compared with an actual value, and the logical threshold voltage of the inverter INV20 is increased. That is, by the testing circuit 300, the data held at the nodes ND110 and ND120 are set to be easily inverted. For this reason, even in the memory cell in which the data is not inverted in the conventional technique, the write data is inverted by the connection of the pre-charged bit line BL20, so that the abnormal state of the memory cell can be detected. Here, the testing circuit 300 pulls up or pulls down the node voltage so that the data is not inverted in a case of the memory cell in the normal state. Thus, according to the method described in the non-patent literature 1, it is possible to detect the memory cell in the abnormal state that cannot be detected in the conventional technique because the SNM is small.
Also, a technique that changes impedance of a load circuit in an inverter of the memory cell so that data held at a node is easily inverted, is described Japanese Patent Application (JP-A-Heisei, 7-182895) (refer to a patent literature 1).
However, in the technique described in the non-patent literature 1, the testing circuit 300 is newly added, thereby increasing the entire circuit area of a semiconductor device. Also, in the technique described in the patent literature 1, it is necessary to insert a load resistance whose impedance is changed on the basis of a test signal, for each memory cell. For this reason, a technique is demanded to detect the memory cell in which the SNM is small and the defect generation probability is high, without any increase in the circuit area.